Scaling of Integrated Circuit Design Including High-Level Logic Components

ABSTRACT

In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.14/677,206, titled “Integrated Circuit Design Optimization,” filed Apr.2, 2015, which is incorporated by reference in its entirety.

BACKGROUND

1. Field of the Invention

This invention relates generally to the optimization of integratedcircuit (IC) designs.

2. Description of Related Art

Integrated circuits and their designs are getting more and more complex.A typical design cycle may last a year or more and costs millions ofdollars. With a long and expensive design cycle, it is important to makeappropriate choices for, among others, process technology and standardcell library.

Traditionally, process technology and cell library are selected manuallybased on past experience. However, such a selection may not actually bethe optimal design point for a particular IC design. This is especiallytrue as the complexity of IC designs increases because, for complexdesigns, it may be more difficult to determine which design points areoptimal, particularly as the number of possible design points alsoincreases.

In addition, as the complexity of IC designs continues to increase, thecost and time associated with fabricating such complex IC designs alsoincreases, thus magnifying the effects of an incorrect choice of processtechnology and/or library.

Therefore, it is important to be able to estimate the performance of ICdesigns before fabricating the IC and also to be able to optimize thedesign based on the estimated performance. It is also important to beable to optimize the performance of the IC design by picking appropriateoptions for process technology and library.

SUMMARY

In one aspect, the present invention overcomes the limitations of theprior art by disclosing approaches for providing design pointrecommendations for an IC design before the actual implementation of thedesign. The method provides the recommendations based on an optimizationof the IC design by automatically selecting appropriate design points(e.g., process technology and/or library) for the IC design in order tomeet or exceed a target PPA (power, performance, and area) metric.

In one embodiment, the following are received by software: the IC designof interest, the desired value of the PPA metric (aka, the target PPAmetric), and the value of the PPA metric evaluated at a reference designpoint (aka, the reference PPA metric). Trial PPA metrics for the ICdesign are estimated at multiple design points. This is done by scalingthe reference PPA metric from the reference design point to the trialdesign point. In one approach, a PPA database contains PPA metrics formultiple test components. Scale factors from the reference design pointto the trial design point are determined for test components that areequivalent to components of the IC design. These scale factors areapplied to the reference PPA metric to determine the trial PPA metricfor the trial design point. One or more of the trial design points arerecommended based on the estimated trial PPA metrics compared to thetarget PPA metric.

Other aspects include different approaches to scaling individualcomponents, including for different types of components such as logiccomponent and memory components. Another aspect includes differentapproaches to scaling IC designs, such as an SoC, which contains manyindividual components. Yet another aspect includes iterativeoptimization of the design point. Yet another aspect includes approachesto scaling an IC design represented at a high level of abstraction wherea logic portion of the IC design is specified as gate count and a memoryportion is specified as actual memory components.

Other aspects include components, devices, systems, improvements,methods, processes, applications and other technologies related to anyof the foregoing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a decision tree showing different design points for a digitalintegrated circuit (“IC”), according to one embodiment.

FIG. 2 is a block diagram illustrating a design engine that recommendsdesign point(s) for a digital IC design, according to one embodiment.

FIG. 3 is a block diagram of the estimation engine shown in FIG. 2,according to one embodiment.

FIG. 4 is a block diagram of the technology logic scaling shown in FIG.3, according to one embodiment.

FIG. 5 is a block diagram of the PVT logic scaling shown in FIG. 3,according to one embodiment.

FIG. 6 is a screen shot illustrating PVT logic scaling, according to oneembodiment.

FIG. 7 is a block diagram of the technology memory scaling shown in FIG.3, according to one embodiment.

FIG. 8 is a block diagram of the PVT memory scaling shown in FIG. 3,according to one embodiment.

FIG. 9 is a block diagram of a special-purpose computing device that canoptimize the IC design, according to one embodiment.

The figures depict various embodiments of the present invention forpurposes of illustration only. One skilled in the art will readilyrecognize from the following discussion that alternative embodiments ofthe structures and methods illustrated herein may be employed withoutdeparting from the principles of the invention described herein.

DETAILED DESCRIPTION

FIG. 1 is a decision tree showing different design points for a digitalintegrated circuit (IC) design 100, according to one embodiment. Adesign point of the decision tree includes a plurality of parametersassociated with optimizing the IC design. The plurality of parameterscan be organized into categories such as technology node parameters,library/memory parameters (depending on the type of component), andoperating conditions parameters.

Technology node parameters include parameters for selecting a nodegeometry, a foundry, and a node variant. Node geometry generallyrepresents a minimum transistor gate length of a process technology usedfor manufacturing semiconductor circuits. For example, node geometry forTSMC 45 nm process technology is 45 nm, which represents the smallestpossible gate length of transistors for that process technology. Examplenode geometries include 90 nm, 65 nm, 45 nm, 28 nm, 22 nm, etc. Foundryis a company that fabricates semiconductor circuits. Example foundriesinclude Taiwan Semiconductor Manufacturing Corporation (TSMC),Semiconductor Manufacturing International Corporation (SMIC), GlobalFoundries (GF), UMC, etc. A node variant is a variation of the processtechnology, typically where some of the properties of the transistorsare optimized for at least one of power, performance, or die area(herein after referred to as “PPA”) metrics. Example node variants forthe TSMC 28 nm process include low power (“LP”), high performance(“HP”), high performance mobile computing (“HPM”), etc. Some otherexample node variants include general purpose (G/GP), low voltage (LV),low power with performance (LPP), low power early (LPE), highperformance with low power (HPL), super low power (SLP), highperformance plus (HPP), FinFet process Plus with low leakage (FPLL),FinFet process with low leakage power (FFLL), General purpose FinFetprocess with low power (FFGL), and FinFet process plus with low power(FPLL).

Library parameters can include a separate set of parameters for logiclibraries. The set of logic parameters include parameters for thelibrary vendor, number of tracks, threshold voltage choice, body bias,and channel length. Library vendor represents a provider of theparticular libraries. Example library vendors include ARM, Dolphin,TSMC, etc. Number of tracks represents a number of horizontal tracksthat can be used for routing. For example, for a given technology node,libraries might be available in 7-track, 8-track, or 9-track variations.Threshold voltage represents a minimum voltage to be applied betweengate and source terminals to create a conducting path between source anddrain terminals. For example, a typical advanced node process includesMOS transistors with low, nominal and high threshold voltages. Anexemplary 40 nm process includes NMOS transistors with thresholdvoltages such as 0.045V, 0.1V, and 0.15V for the low VT, standard VT andhigh VT device respectively. It is understood that the threshold voltagevaries with device size and the above-listed exemplary values are forone specific device size. Channel length represents a minimum distancebetween source and drain terminals of a MOS transistor. An exemplaryadvanced node CMOS process includes MOS transistors with short, standardand long channel length transistors.

Memory parameters can include memory compilers, number of ports, type ofport (read/write), number of words in memory, number of bits per word,mux (how the words are organized), banks (how a memory sub array isorganized), redundancy—provides additional rows or columns in the memoryarray for repair, pipeline—enables pipelining of memory output,BIST—includes Built-In-Self-Test logic or hooks to such test logic, andpower management features that enable the memory to conserve power whennot in operation.

Operating condition parameters include parameters for estimating aperformance of the IC design at various possible operating conditions.Such operating condition parameters can represent process, voltage, andtemperature (also known as “PVT”). Process represents the possiblevariations of the process technology when the IC design is beingmanufactured. The possible variations of MOS transistors, capacitors,resistors, etc., are represented by process corners. Example processcorners include SS (slow NMOS and slow PMOS transistors), FF (fast NMOSand fast PMOS transistors), and TT (typical NMOS and typical PMOStransistors).

Voltage represents a supply voltage (“VDD”) of the IC design that canfurther represent a maximum amount of voltage available for a signalthat is processed by the IC design. For example, when the referencevoltage of the IC design is a ground that is assigned zero volts, avalue of VDD represents the supply voltage. Even though VDD is designedto be a fixed number (e.g., 1V), the value of VDD varies due to manyfactors and VDD typically has some variation such as +/−10%. Forexample, when VDD is designed to have a nominal value of 1V, VDD valuescan be as low as 0.9V and as high as 1.1V. Temperature parameterrepresents a junction temperature for the operation of the IC design.Depending on the application of the IC design, the IC design should meetor exceed its performance specification over a range of junctiontemperatures. For example, a common range of junction temperaturespecification is between −40° C. to +125° C.

The IC design 100 is optimized, in part by picking an appropriatecombination of various parameters (a design point), such that estimatedPPA metrics at the design point will meet or exceed a PPA target.Exemplary PPA metrics include power consumption (e.g., dynamic power andleakage power), performance (e.g., operating frequency), and silicon diearea for manufacturing the IC design. A design point does not have toinclude all of the parameters shown. For example, earlier in the designprocess, the design point might include a fewer number of moresignificant parameters. Later in the design process, the design pointmight include a larger number of parameters. The design point also isnot limited to the specific parameters shown.

FIG. 2 is a block diagram illustrating a design engine that recommendsdesign point(s) for a digital IC design, according to one embodiment.FIG. 2 shows IC design engine 250 that receives an IC design 200 alongwith reference PPA metric 214, a target PPA metric 210, and designconstraints 212. The IC design engine processes the received informationand uses information available in PPA database 290 to providerecommended design point(s) 280 as an output of the IC design engine.

The IC design is a design for which a user is expecting the IC designengine to recommend appropriate design points that meet or exceed targetPPA metric 210. The received IC design can be a synthesized netlist oran RTL-level description. In one embodiment, the received IC design is adesign for a system-on-chip (SoC). The IC design typically includes aplurality of blocks, for example, Blocks 1 through N. Each block of theplurality of blocks can comprise a plurality of sub-blocks and/orcircuit components, including one or more logic components and one ormore memory components as shown below in FIG. 3.

In one embodiment, an IC design block is defined as a portion of the ICdesign where the entire block uses the same library group. In thisexemplary embodiment, a library group is defined to include a group ofdesign points with a specific technology node, a specific libraryvendor, and a specific number of routing tracks. For example, all thelibrary variants within a 40 nm TSMC LP process with a Dolphin librarywith 9-tracks is considered to be a library group. Each library groupcan include several library variants. A library variant can includedifferent combinations of parameters such as channel length andthreshold voltage. More generally, a library group can be defined as theset of libraries that are “compatible” with each other when implementingan IC design block. That is, the group of library variants that can bemixed when implementing an IC design block is referred to as a librarygroup. In one embodiment, library groups are pre-determined anddifferent library groups can be chosen for each IC design block.

Reference PPA metric 214 is also received along with the IC design.Reference PPA metric 214 is determined by evaluating the IC design at areference design point. For example, the IC design is evaluated bypassing it through a more complete digital design flow at the referencedesign point. The reference design point typically includes a value foreach of the technology node parameters, library/memory parameters, andoperating conditions parameters. In one embodiment, the reference designpoint is at standard PVT conditions. Alternatively, the reference designpoint is at PVT conditions other than at standard PVT conditions.

The target PPA metric 210 is a PPA metric that the user wants the ICdesign to meet or exceed, as the IC design engine is estimating PPAmetrics for the IC design 200 at various design points. That is, the ICdesign engine uses the target PPA metric 210 to determine whether aparticular design point is to be recommended for the IC design. TargetPPA metric 210 can include at least one of a power metric, a performancemetric, and an area metric. For example, the power metric can includedynamic power consumption and/or leakage power consumption of the ICdesign. The performance metric can include, for example, an operatingfrequency of the IC design. The area metric can include, for example, asilicon die area for the IC design. In one embodiment, target PPA metric210 includes all metrics associated with power, performance, and area.Alternatively, target PPA metric 210 includes one of either a powermetric, a performance metric, or an area metric. Yet in anotherembodiment, target PPA metric 210 includes any two metrics associatedwith power, performance, and area.

Design constraints 212 can include one or more conditions on the designpoints. For example, design constraints 212 can include a condition thata range of allowed supply voltage for the IC design should be +/−10%from the nominal value. Accordingly, the IC design engine would applythe condition on supply voltage as an additional criterion in additionto optimizing the parameters used for each design point in complyingwith the target PPA metric 210. For example, the IC design engine mightonly consider design points that have a supply voltage variation of lessthan or equal to +/−10% as specified by design constraints 212. It isunderstood that design constraints 212 can specify conditions on any ofthe parameters, as described above with reference to FIG. 1, associatedwith technology node parameters, library/memory parameters, andoperating conditions parameters. The design constraints 212 can alsospecify other conditions. For example, design constraints 212 caninclude a target operating frequency that is typically specified as atiming constraint on the design.

The IC design engine 250 receives the IC design 200 along with areference PPA metric 214 evaluated at a reference design point. The ICdesign engine 250 also receives any applicable design constraints 212.To provide recommended design point(s) 280, the IC design engine 250optimizes the design points. In the example of FIG. 2, the design engine250 selects 260 a trial design point and estimates 270 the PPA metric ofthe IC design at the selected trial design point. The trial design pointcan be any design point in the available design space.

In one exemplary embodiment, the IC design engine 250 iterativelyoptimizes the design point. It selects 260 a trial design point and thenestimates 270 the PPA metric at the selected trial design point. Basedon the estimates 270, the IC design engine 250 iterates 260 the trialdesign point by varying one or more parameters associated withoptimizing the IC design and then recalculates 270 the PPA metric. Thisiteration continues until a suitable design point is determined andrecommended 280.

In another exemplary embodiment, the IC design engine 250 repeats theprocess of selecting 260 a trial design point and estimating 270 the PPAmetric at the selected trial design point for all applicable designpoints. That is, the IC design engine 250 explores the possible designspace by performing an exhaustive search. The IC design engine 250 thenrecommends 280 design points based on the exhaustive search. In onevariation, the IC design engine 250 samples the design space but doesnot necessarily estimate 270 the PPA metric for every possible designpoint.

The IC design engine estimates 270 the PPA metric at each selected trialdesign point by referring to PPA database 290. The reference PPA metric214 is typically evaluated at the reference design point by using a morecomplete or accurate method than the one used by IC design engine 250.For example, the reference PPA metric 214 may be evaluated by passingthe IC design through a complete design flow. In comparison, the ICdesign engine 250 uses the information in PPA database 290 to determinescale factors for scaling from the reference design point to the trialdesign point. These scale factors are applied to the reference PPAmetric 214 to estimate the trial PPA metric 270.

PPA database 290 is a database that includes data associated with PPAmetrics of multiple test components evaluated at multiple design points.Consider logic components as an example, although similar remarks applyto memory or other components. The design points at which the PPAmetrics are evaluated preferably include a sufficient sampling of valuesfor technology node parameters (i.e., node geometry, foundry, and nodevariants), library groups (e.g., library vendors and number of tracks),library variants (e.g., threshold voltage and channel length), and PVTconditions. For example, a test component such as a 32-bit multipliercan be evaluated at different design points in a design space that spansall of the parameters described in FIG. 1. Test components are circuits(e.g., logic in this example) at either transistor-level, gate-level,and/or block-level that are evaluated for various PPA metrics atdifferent design points in the design space. The test components areevaluated before receiving the IC design 200. That is, PPA database 290is constructed a priori.

The data of the PPA database includes a value of an evaluated PPA metricthat is evaluated at different design points for the test components.For example, if each of the ten parameters of the design pointsdescribed in FIG. 1 are sampled at two different values, there would bea total of 1024 (i.e., 2¹⁰) possible design points represented in thePPA database. The exemplary test component, a 32-bit multiplier, has aPPA metric for each of power, performance, and area. For this exemplarycase, the PPA database includes 1024 values for each of power,performance, and area PPA metric for the 32-bit multiplier for the 1024possible design points. Similarly, the PPA database includes evaluatedPPA metrics for other test components. Data included in the PPA databaseis generated at a time prior to receiving the IC design such that alldata associated with PPA database is already available when the ICdesign engine receives the IC design. Although this example concernslogic, the PPA database 290 includes data associated with both logic andmemory as described below in detail with reference to FIGS. 4-8.

Continuing the logic example, after selecting 260 a trial design point,the IC design engine 250 identifies one or more test components in thePPA database 290, that are equivalent to the logic in the received theIC design, at least for purposes of estimating the PPA metric. Thedesign engine 250 accesses the PPA database 290 for the evaluated PPAmetrics of the identified test components at the selected trial designpoint. The design engine determines scale factors for the one or moretest components, for scaling from the reference design point to thetrial design point. The design engine estimates trial PPA metric of thereceived IC design by applying the determined scale factors to thereference PPA metrics of the received IC design.

In one embodiment, the design engine estimates trial PPA metric of thereceived IC design at a block-level. That is, the design engineimplements estimating of trial PPA metric of the IC design for eachblock of the plurality of blocks of the IC design, and later combinesthe trial PPA metrics of each block to generate an estimate for trialPPA metric of the entire IC design for the selected trial design point.The process of estimating trial PPA metric at a block-level is describedbelow in FIGS. 3-8.

The design engine 250 generates recommended design point(s) 280 based onthe estimated trial PPA metric at each selected trial design and thereceived target PPA metric. For example, if the target metric is for atarget silicon die area, the design engine would recommend trial designpoints based on whether the estimated silicon die area that is less thanor equal to the target die area. If the target metric is for a targetoperating frequency, the design engine would recommend trial designpoints based on whether the estimated operating frequency is greaterthan or equal to the target operating frequency. And if the targetmetric is for a target power consumption (leakage or dynamic), thedesign engine would recommend trial design points based on whether theestimated power consumption is less than or equal to the target powerconsumption.

The recommended design points can also be based on the received designconstraints 212. For example, the recommended design points can be basedon design constraints associated with at least one of: foundrymanufacturers, node geometries, and library vendors.

In one embodiment, the recommended design point includes a trial designpoint that meets or exceeds the target PPA. Alternatively, therecommended design points include all trial design points that meet orexceed the target PPA. The recommended design point is output in theform of a table. Each entry in the table corresponds to a design pointand includes the PPA metrics associated with that design point. Eachdesign point of the recommended design points can include all parametersdescribed above with reference to FIG. 1. In one embodiment, each designpoint of the recommended design points includes all ten parametersassociated with technology node parameters, library/memory parameters,and operating conditions parameters described in FIG. 1. Alternatively,each design point of the recommended design points includes a subset ofall ten parameters described in FIG. 1. For example, each design pointof the recommended design points can include one or more of: foundries,node geometries, node variants, library vendors, number of tracks,threshold voltage, channel length, and operating conditions includingprocess, voltage, and temperature. These parameters are for logiccomponents. Since the IC design usually contains both memory and logic,each design point will typically also include memory parameters inaddition to the standard cell library parameters. Design parametersother than those shown in FIG. 1 can also be used.

FIG. 3 is a block diagram of the estimation engine 270 shown in FIG. 2,according to one embodiment. FIG. 3 shows estimation engine 270 thatreceives blocks of the IC design to estimate a trial PPA metric at aselected trial design point. In addition to receiving blocks of ICdesign, estimation engine 270, as discussed above with reference to FIG.2, also receives a reference PPA 214 evaluated at a reference designpoint and the trial design point at which the trial PPA is to beestimated. The estimation engine estimates trial PPA metrics for ICdesign blocks using a number of modules such as segmentation module 320,technology logic scaling module 372L, PVT logic scaling module 374L,technology memory scaling module 372M, PVT memory scaling module 374M,and combiner module 380.

The term “module” is not meant to be limited to a specific physicalform. Depending on the specific application, modules can be implementedas hardware, firmware, software, and/or combinations of these. In someembodiments, the modules are implemented as dedicated circuitry (e.g.,part of an ASIC), in order to take advantage of lower power consumptionand higher speed. Alternatively, the modules can be implemented assoftware, typically running on digital signal processors or evengeneral-purpose processors. Various combinations can also be used. Forexample, certain operations, like reading and writing from the PPAdatabase, may be common enough as to be available as standardcomponents, software, or circuit designs. These may be combined withcustomized implementations of the remainder of the estimation engine.Furthermore, different modules can share common components or even beimplemented by the same components. There may or may not be a clearboundary between different modules. In this example implementation, themodules shown are implemented as software modules.

Segmentation module 320 receives an IC design block and partitions itinto one or more logic components and one or more memory components. TheIC design comprises a plurality of blocks as described above withreference to FIG. 1. Each block of the IC design can further comprise aplurality of circuit components. Circuit components can include logiccomponents and/or memory components. For example, Block 1 of FIG. 3comprises K logic components labelled L1-LK and N memory componentslabelled M1-MN. One method of partitioning preserves the inherentpartitioning of the IC design block into logic and memory componentsthat is already present in the IC design block. This inherentpartitioning is defined, for example, in the RTL or netlist of the ICdesign block.

The estimation engine estimates trial PPA for each IC design block(trial block-level PPA metric) by estimating trial component-level PPAmetrics for the circuit components at the trial design point. Modules372L and 374L estimate trial component-level PPA metrics for logiccomponents, and modules 372M and 374M estimate trial component-level PPAmetrics for memory components. The engine then combines (e.g., viacombiner module 380) the estimated trial logic PPAs and the trial memoryPPAs to generate an estimated trial block-level PPA and/or an estimatedtrial PPA metric for the entire IC design at the trial design point.

The logic components are passed through scaling processes to estimatethe PPA metrics of the logic components at the trial design point, basedon the known PPA metric at the reference design point. The scalingprocess between the reference and trial design points can be implementedby selecting an appropriate test component whose PPA metrics havealready been evaluated at different design points. The scaling of thelogic components is implemented by passing it through technology logicscaling module 372L and PVT logic scaling module 374L to estimate atrial logic PPA for each logic component. In one embodiment, technologylogic scaling accounts for any differences in one or more of thetechnology node parameters (i.e., node geometry, foundry, and nodevariants), library groups (e.g., library vendors and number of tracks),and library variants (e.g., combinations of channel length and thresholdvoltage for a given library group). PVT logic scaling accounts for anydifferences in operating conditions (i.e., PVT conditions). In otherwords, technology logic scaling first performs logic scaling of thelogic components with respect to changes in technology node parameters,library groups, and library variants, and PVT logic scaling thenperforms logic scaling with respect to changes in PVT conditions. Thetrial logic PPAs from technology and PVT logic scaling are combined togenerate estimated trial block-level logic PPAs for the IC design block.

The technology logic scaling module 372L selects one or more technologylogic test components (from PPA database 290) based on a similaritybetween the logic components of the IC design block and the technologylogic test components. The logic components in the IC design typicallyare not the same components as the test components that arepre-evaluated to generate the PPA database. Typically, the number ofdifferent logic components in the IC design (e.g., in a given block orthe entire IC design) is greater than the number of different technologylogic test components used to generate the PPA database. The process ofselecting appropriate technology logic test components is described indetail below with reference to FIG. 4.

Technology logic scaling module 372L accesses the PPA database 290 foridentifying the evaluated PPA metrics of the selected technology logictest component at both the reference and trial design points. The module372L determines a technology logic scale factor for the technology logictest component, for scaling from the reference design point to the trialdesign point. The technology logic scale factors between differentdesign points in the design space are calculated for each of thetechnology logic test components before receiving the IC design.

The PVT logic scaling module 374L selects a PVT logic test componentbased on the technology node parameters and library parameters of thetrial design point. For example, if the trial design point specifiesTSMC 45 nm HPM (High-Performance Mobile) process with TSMC models having9-tracks, an appropriate PVT logic test component (e.g., NAND2 gate)that was implemented in the above-specified exemplary technology nodeparameters and library parameters is selected for PVT logic scaling. ThePVT logic scaling module accesses the PPA database 290 for identifyingthe evaluated PPA metrics of the selected PVT logic test component atthe reference and trial design points. The PVT logic scaling module thendetermines a PVT logic scale factor for the PVT logic test component,for scaling from the reference design point to the trial design point.The process of generating PVT logic scale factors for each logiccomponent of the IC design block is described below in detail withreference to FIG. 5.

The technology and PVT logic scale factors are applied to the referencelogic PPAs of the logic components to generate trial logic PPAs for thecomponents at the trial design point.

The memory components of the IC design block are passed throughtechnology memory scaling module 372M and PVT memory scaling module 374Mto estimate a trial memory PPA for each memory component. Memory scalingdiffers from logic scaling in the following manner. Scaling of a logiccomponent is based on a test component from the PPA database that isrepresentative of the actual logic component but that typically is notthe actual logic component. Scaling of a memory component is based onscaling the actual memory component itself. That is, the test componentfrom the PPA database is the memory component itself. If the PPAdatabase does not contain the actual memory component, it can be createdin real-time and its PPA metrics are generated in real time as well. Theprocess of memory scaling is described below in detail with reference toFIGS. 7 and 8. The technology and PVT memory scale factors determinedfor the memory components uses a procedure that is different from theprocedure used to determine scale factors for the logic components.

The trial component-level PPA metrics estimated by modules 372-374 arecombined by combiner module 380 to generate estimated trial logic PPAsfor the IC design block. In one approach, for each component of the ICdesign block, module 380 combines the trial component-level PPA metricsfor both logic and memory to obtain trial block-level PPA metrics. Thesetrial block-level PPA metrics can be combined by module 380 to obtainthe trial PPA metric for the IC design.

The combination process depends on the PPA metric for which the ICdesign is optimized for. For example, if the PPA metric is powerconsumption (either leakage power or dynamic power), the trial power PPAmetric for the IC design is estimated by first summing the trialcomponent-level power PPA metrics to obtain trial block-level power PPAmetrics and then by summing the trial block-level power PPA metrics toobtain the trial power PPA metric for the entire IC design. If the PPAmetric is performance (e.g., operating frequency), the trial performancePPA metric for the IC design is estimated by first selecting theworst-case trial component-level performance PPA metric (i.e., lowestoperating frequency at the component-level) to obtain trial block-levelperformance PPA metric and then by further selecting the worst-casetrial block-level performance PPA metric to obtain the trial performancePPA metric for the entire IC design. If the PPA metric is area (i.e.,silicon die area), the trial area PPA metric for the IC design isestimated by first summing the trial component-level area PPA metrics toobtain trial block-level area PPA metrics and then by summing the trialblock-level area PPA metrics to obtain the trial area PPA metric for theentire IC design.

In one exemplary embodiment, during calculating trial PPA metrics forthe IC design and also during recommending design points for the ICdesign, all blocks are assigned the same node geometry and foundry, butdifferent blocks can be assigned to different library groups. In theabove exemplary embodiment, all logic components within a given blockare assigned the same library group, but can be assigned differentlibrary variants within the library group.

In another variation, PPA metrics are evaluated at an early designstage, when the actual logic design is not yet known. The logic portionof the IC design 200 is represented by a number of logic gates insteadof being represented by the actual logic components. That is, the logicportion is represented by a logic gate count at a high level ofabstraction. Logic scaling then proceeds as described above, usingrepresentative logic test components from the PPA database. The memoryportion of the IC design 200 is represented by memory components, asdescribed above, and memory scaling proceeds as described above.

As discussed above with reference to FIG. 2, an IC design block can bedefined in part as a circuit of the IC design at a hierarchy level ofthe IC design where the entire block uses the same library group, wherethe library group is defined as the set of libraries which have the sametechnology node, library vendor and number of routing tracks. One methodof optimizing blocks of IC design is as follows. First, availablelibraries are sorted into library groups. In one embodiment, the sortingof the libraries into library groups is predetermined based on thetechnology node. Next, one or more candidate library groups are selectedfor each block of the IC design. Each library group includes libraryvariants including different combinations of parameters such as channellength and threshold voltage. One way of selecting candidate librarygroups for each block is by ensuring that a PPA metric of the blockcorresponding to at least one library variant in a candidate librarygroup exceeds a target PPA metric for the block. Next, scale factors forPPA metrics are calculated for each of the candidate library groups.Then, PPA metrics for the block are calculated by applying the scalefactors corresponding to each candidate library group. Finally, one ofthe candidate library groups is selected for the block, includingaccounting for any design constraints 212. For example, if the designconstraints include minimizing area PPA, the candidate library groupthat provides for the smallest estimated area PPA for the block isselected. The design engine can output a table to list all candidatelibrary groups and their corresponding estimated PPA metrics for eachblock.

In some embodiments, more than one library variant can be used withinthe same IC design block to achieve optimal PPA metrics for the block.For example, let us assume that a block has N gates, has a target PPAmetric of G, and achieves a relative speed up S_UP (compared with areference design point) with a fast library and a relative slow downS_DN with a slow library. One way to optimize the performance PPA ofsuch an exemplary block is by choosing the fast library for some portionof the gates of the block and choosing the slow library for theremaining portion of the blocks. If the number of gates to beimplemented using the fast library is n, the ratio n/N is the portion ofthe gates implemented in the fast library. An exemplary equation toachieve the target performance is given by:

$\begin{matrix}{{{\frac{n}{N}{S\_ UP}} + {\frac{N - n}{N}{S\_ DN}}} = G} & (1)\end{matrix}$

Solving for n/N yields

$\begin{matrix}{\frac{n}{N} = \frac{G - {S\_ DN}}{{S\_ UP} - {S\_ DN}}} & (2)\end{matrix}$

FIG. 4 is a block diagram of the technology logic scaling 372L shown inFIG. 3, according to one embodiment. Technology logic scaling module372L receives a logic component, for which to estimate component-leveltrial logic PPA metric for the logic component at a trial design point.The technology logic scaling module estimates the component-level triallogic PPA metric by referring to technology logic PPA database 292L. Themodule also receives a reference PPA metric associated with the receivedlogic component that is based on the reference PPA 214.

In one embodiment, technology logic scaling accounts for differences inone or more of the technology node parameters (i.e., node geometry,foundry, and node variants), library groups (e.g., library vendors andnumber of tracks), and/or library variants (e.g., channel lengths andthreshold voltages). In other words, technology logic scaling performslogic scaling of the logic components over technology node parameters,library groups, and library variants. Accordingly, the trial designpoint used for technology logic scaling can use the reference designpoint values for PVT conditions.

The reference design point used in generating reference PPA 214 of thelogic component includes a first set of values (the reference values)for technology node parameters (i.e., node geometry, foundry, and nodevariants), library groups (e.g., library vendors and number of tracks),and library variants (e.g., channel lengths and threshold voltages). Forthe parameters of PVT conditions, the reference design point alsoincludes values corresponding to the first set of values of technologynode parameters, library groups, and library variants. Often, these arestandard values. For example, if the reference values for technologynode parameters, library groups, and library variants are 45 nm TSMC HPMprocess technology with 8-track TSMC models operating at channel lengthof 45 nm and threshold voltage of 0.3V, the parameters for PVTconditions will include the nominal values associated with the 45 nmTSMC HPM process technology with 8-track TSMC models. In one embodiment,the nominal values for the PVT conditions of 45 nm TSMC HPM processtechnology with 8-track TSMC models are room temperature (e.g., 25 C),nominal supply voltage (e.g., 1V), and nominal process corner (e.g.,typical process corner).

The trial design point used for estimating trial PPA of the logiccomponent includes a second set of values (the trial values) fortechnology node parameters, library groups, and library variants. Forthe parameters of the PVT conditions, the trial design point uses thesame values as the reference design point. For example, if the trialvalues for technology node parameters and library groups are 28 nm TSMCHPM process technology with 8-track TSMC models operating at channellength of 35 nm and threshold voltage of 0.2V, the parameters for thePVT conditions will include the nominal values associated with the 28 nmTSMC HPM process technology with 8-track TSMC models operating atchannel length of 35 nm and threshold voltage of 0.2V. In oneembodiment, the nominal values for the PVT conditions for theseparameters are room temperature (e.g., 25 C), nominal supply voltage(e.g., 0.9V), and nominal process corner (e.g., typical process corner).Alternatively, the trial design point can use the nominal parametervalues of the reference design point, as described above, for the PVTconditions.

Technology logic PPA database 292L is a subset of PPA database 290. Thetechnology logic PPA database includes evaluated PPA metrics oftechnology logic test components at various design points. The designpoints at which the PPA metrics are evaluated include different valuesfor technology node parameters (i.e., node geometry, foundry, and nodevariants), library groups (e.g., library vendors and number of tracks),and library variants (e.g., channel lengths and threshold voltages). Forthe parameters of the PVT conditions, the design points include standardvalues corresponding to each set of values of the technology nodeparameters and library parameters (i.e., library groups and libraryvariants). Because technology logic scaling accounts for differences inthe technology node parameters, library groups, and library variants,the technology logic PPA database typically does not need to includeevaluated PPA values of the technology logic test components for the PVTconditions at other than standard values corresponding to a set ofvalues of technology node parameters, library groups, and libraryvariants.

The technology logic PPA database 292L includes evaluated PPA metricsfor a plurality of technology logic test components. One method tochoose the individual technology logic test components of the pluralityof technology logic test components is to use a test component that issimilar to the actual logic component in the IC design block, wheresimilarity is determined based on a set of properties. An exemplary listof properties include logic depth, fanout, wire length per fanout, andthe like. An exemplary list of technology logic test components caninclude: memory controllers such as double data rate (DDR) memorycontroller and direct memory access (DMA) controller, data encryptionstandard (DES) circuits, advanced encryption standard (AES) circuits,joint photographic experts group (JPEG) encoder, JPEG decoder,multiplier circuits such as a 32-bit multiplier, universal asynchronousreceiver/transmitter (UART) peripheral, and synchronous serialperipheral. It is understood that additional and/or alternate circuitsto that of the above-referenced exemplary list of technology logic testcomponents can be added to the plurality of technology logic testcomponents.

The technology logic PPA database is generated by characterizing varioustechnology logic test components at different design points. One methodof characterizing the technology logic test components is by startingwith an RTL design of the technology logic test component, synthesizingthe RTL design and performing a layout using conventional electronicdesign automation (EDA) tools such as Talus by Synopsys™. In oneembodiment, each technology logic test component is characterized byevaluating its PPA metrics at different design points of the designspace. An exemplary technology logic test component, a DDR controller,can have PPA metrics for power, performance, and area. The PPA metricscan be evaluated at design points that sample a large design space, asmaller design space or a portion of a design space. For example, whenthe technology is fixed as TSMC 28 nm, the number of variable designparameters is reduced.

The technology logic scaling process begins by identifying 410 whichtechnology logic test component(s) will be used to evaluate the receivedlogic component. This will be referred to as the equivalent technologylogic test component. In one approach, the equivalence is determined byusing logic parameters. Logic parameters for the received logiccomponent are calculated. The calculated logic parameters can include,for example, a logic depth of the logic component, a fanout of the logiccomponent, a wire length per fanout of the logic component, and thelike.

The technology logic scaling module identifies 410 an equivalenttechnology logic test component based on the calculated logicparameters. In some embodiments, the module can compute a similarityfactor between the received logic component and each of the technologylogic test components by weighting different logic parameters of thereceived logic component. The module then uses the computed similarityscore to identify an equivalent technology logic test component by, forexample, selecting a technology logic test component that has theclosest similarity score to the received logic component. In someembodiments, the module identifies two or more of the technology logictest components based on the similarity score. For example, the modulecan identify the technology logic test components with the two closestsimilarity scores and then apply a weighting factor for each. Thereceived logic component is not the same as its equivalent technologylogic test component.

Technology logic scaling module 372L accesses technology logic PPAdatabase 292L for identifying the evaluated PPA metrics of thetechnology logic test components at the reference and trial designpoints. The module then determines a technology logic scale factor forthe technology logic test component, for scaling from the referencedesign point to the trial design point. In one embodiment, the moduleuses the evaluated PPA metrics of the technology logic test component atthe reference design point and at the trial design point to determinethe technology logic scale factor of the technology logic testcomponent. For example, the module identifies a first value for theevaluated PPA metric of the technology logic test component at thereference design point and a second value at the trial design point. Themodule then computes a ratio of the first and second values to determinethe technology logic scale factor for the technology logic testcomponent. For example, a ratio between first and second values of PPAmetrics is 1.1.

The technology logic scale factor determined for the technology logictest component is then applied to the reference PPA of the receivedlogic component to generate an estimated technology trial logic PPA ofthe logic component at the trial design point. For example, if thereference area PPA for the logic component is 1000 μm² and if thetechnology logic scale factor is 1.1, the estimated technology triallogic area PPA of the logic component at the trial design point is 1100μm² (i.e., 1000 multiplied by 1.1). As another example, if the referenceperformance PPA (e.g., operating frequency) for the logic component is 1GHz and if the technology logic scale factor is 1.2, the estimatedtechnology trial logic performance PPA of the logic component at thetrial design point is 0.833 GHz (1 GHz divided by 1.2).

FIG. 5 is a block diagram of the PVT logic scaling shown in FIG. 3,according to one embodiment. PVT logic scaling module 374L receives thelogic component to estimate component-level trial logic PPA metric forthe logic component at a trial design point. The PVT logic scalingmodule estimates the component-level trial logic PPA metric by referringto PVT logic PPA database 294L. The module also receives a PPA metric420 that is the estimated technology trial logic PPA metric by thetechnology logic scaling module for the received logic component.

In one embodiment, PVT logic scaling accounts for differences in theoperating conditions (i.e., PVT conditions). Technology logic scaling,as described above with reference to FIG. 4, accounts for differences intechnology node parameters (i.e., node geometry, foundry, and nodevariants), library groups (e.g., library vendors and number of tracks),and library variants (e.g., channel lengths and threshold voltages). Inother words, technology logic scaling first performs scaling of thelogic components over technology node parameters, library groups, andlibrary variants, and PVT logic scaling then performs scaling over PVTconditions.

The received PPA metric 420 is an estimated technology logic PPA metricfor the logic component at the trial design point. The variousparameters of the design point associated with the PPA metric 420 arethe same as the trial design point used in technology logic scalingmodule 372L. The parameters include the trial values (described abovewith reference to FIG. 4) for technology node parameters, librarygroups, and library variants, and standard (or nominal) values for thePVT conditions. For example, as described above with reference to FIG.4, if the trial values for technology node parameters, library groups,and library variants are 28 nm TSMC HPM process technology with 8-trackTSMC models operating at a channel length of 35 nm and threshold voltageof 0.2V, the parameters for the PVT conditions include the nominalvalues associated with these parameters, such as room temperature (e.g.,25 C), nominal supply voltage (e.g., 0.9V), and nominal process corner(e.g., typical process corner).

The trial design point of the PVT logic scaling used for estimatingtrial PPA of the logic component includes the same trial values fortechnology node parameters, library groups, and library variants as usedin the trial design point for technology logic scaling. The trial designpoint of the PVT logic scaling includes trial values for the parametersof the PVT conditions. For example, for the second set of values fortechnology node parameters, library groups, and library variants of 28nm TSMC HPM process technology with 8-track TSMC models operating at achannel length of 35 nm and threshold voltage of 0.2V, the parametersfor the PVT conditions will include trial values for temperature, supplyvoltage, and process corner.

PVT logic PPA database 294L is a subset of PPA database 290. The PVTlogic PPA database includes evaluated PPA metrics of PVT logic testcomponents at various design points. The PVT logic test components thatare used in generating the PVT logic PPA database include different testcomponents for different sets of technology node parameters, librarygroups and library variants. For example, for a 28 nm TSMC HPM processtechnology with 8-track TSMC models, a NAND logic gate implemented in 28nm TSMC HPM process technology with an 8-track TSMC library is theselected PVT logic test component. For a 45 nm TSMC LP processtechnology with 8-track TSMC models, a NAND gate implemented in 45 nmTSMC LP process technology with an 8-track TSMC library is the selectedPVT logic test component. Accordingly, there can be a different PVTlogic test component for each combination of technology node parameters,library groups, and library variants. In some embodiments, logic gatesother than a NAND gate such as a NOR gate can be used as PVT logic testcomponents. Alternatively, PVT logic test components can be implementedat a MOS transistor level as well.

The design points at which the PPA metrics of the PVT logic PPA databaseare evaluated include different values for technology node parameters,library groups, library variants, and PVT conditions. One method ofgenerating the PVT logic PPA database is to first identify the number ofunique PVT logic test components (e.g., F) that are needed based on thenumber of unique combinations of technology node parameters, librarygroups, and library variants. For example, there can be F number of2-input NAND gates. In such exemplary embodiment, each of the F numberof NAND gates is evaluated at different combinations of parametersassociated with the PVT conditions. Given that there are threeparameters associated with the PVT conditions (i.e., process corner,supply voltage, and temperature), each NAND gate might be evaluated N³times, where N is the number of possible values for each of the threeparameters. Additional logic parameters such as fan-out can also be usedto evaluate the PVT logic components.

The PVT logic PPA database is generated by characterizing various PVTlogic test components at different design points. One method ofcharacterizing the logic test components (e.g., NAND gate) is bysimulating the NAND gate to evaluate its PPA metrics at different designpoints. The PPA metrics that are evaluated can include, for example,delay, slew rate, active power consumption, leakage power consumption,and area. Each of the above-listed NAND gate PPA metrics is evaluatedfor various values of parameters associated with the PVT conditions. Forexample, NAND gate PPA metrics can be evaluated at different junctiontemperatures, process corners, supply voltage, and fanout.

The PVT logic scaling process begins by the PVT logic scaling moduleselecting an appropriate PVT logic test component (e.g., an appropriateNAND gate) based on the given technology node parameters, library groupparameters, and library variant parameters of the trial design pointused for technology logic scaling. The module then accesses the PVTlogic PPA database to identify 510 PPA metrics of the selected NAND gatefrom the PVT logic PPA database 294L. The module identifies PPA metricsfor two sets of values for the parameters of the PVT conditions. Thefirst set of values corresponds to the standard (or nominal) values ofthe parameters of the PVT conditions associated to the received PPA 420from the technology logic scaling. The second set of values correspondsto the trial values of the parameters of the PVT conditions associatedwith the trial design point.

The module then determines 512 a PVT logic scale factor for the NANDgate between the first set of values and the second set of values. Forexample, the module computes a ratio of the first and second values todetermine the PVT logic scale factor for the logic test component. Forexample, a ratio between first and second values of PPA metrics might be1.02.

The PVT logic scale factor determined for the logic test component isthen applied to scale 514 the received technology logic PPA 420 of thelogic component to generate an estimated trial logic PPA of the logiccomponent at the trial design point. For example, if the receivedtechnology area PPA for the logic component is 1100 μm² and if the PVTlogic scale factor is 1.02, the estimated trial logic area PPA of thelogic component after PVT logic scaling at the trial design point is1122 μm² (i.e., 1100 multiplied by 1.02). As another example, if thereceived technology performance PPA (e.g., operating frequency) for thelogic component is 0.8 GHz and if the PVT logic scale factor is 0.97,the estimated trial logic performance PPA of the logic component afterPVT logic scaling at the trial design point is 0.86 GHz (i.e., 0.833divided by 0.97). The estimated trial logic PPA at the output of PVTlogic scaling module is a trial logic PPA of the logic component aftercombining the technology logic scaling and the PVT logic scaling.

FIG. 6 is a screen shot 600 illustrating another application of PVTlogic scaling, according to one embodiment. The screenshot includes atool bar 610 that includes different options for a user. For example,tool bar 610 includes an option 612 for estimating Scale Factors. Thescale factor calculator has options 620 to select a particular processtechnology (e.g., CLN28HPM), library vendor (e.g., TSMC), and number oftracks (e.g., 9). For a combination of selected values of options 620,the calculator also includes options 630 to select channel length (e.g.,default value of 35 nm) and threshold voltage class (e.g., SVT, LVT, andULVT for channel length of 30.6 nm) to enable the scaling module toselect the appropriate NAND gate for determining the PVT scale factors.Options 630 also includes an option to select either power or frequencyas the default PPA metric to be evaluated.

Options 630 further includes an input for a baseline PVT reference(e.g., FF process corner, 0.99V supply voltage, and 125 C temperaturefor power PPA) and a set of trial PVT conditions for which scale factorsare to be calculated. In this screen shot, the trial PVT conditions arecurrently set the same as the PVT reference. After an appropriate NANDgate is selected, and inputs for baseline and trial PVT conditions arereceived, the scaling module calculates scale factors between thebaseline PVT conditions and trial PVT conditions. The scaling module cancalculate a scale factor for each of power, performance, and areametrics. In the exemplary screenshot, the scaling module depicts a scalefactor for active power, leakage power, and frequency, which are all setto 1.0000 because the baseline and trial PVT parameters are currentlyset the same. In the actual optimization implementation, the scalefactor calculation is performed by software. The user interfacepresented in the screenshot is intended primarily for design explorationfor users.

FIG. 7 is a block diagram of the technology memory scaling shown in FIG.3, according to one embodiment. Technology memory scaling module 372Mreceives a memory component to estimate component-level technology trialmemory PPA metric for the memory component at a trial design point. Thetechnology memory scaling module estimates the component-leveltechnology trial memory PPA metric by referring to technology memory PPAdatabase 292M. The module also receives a reference PPA metricassociated with the received memory component that is based on thereference PPA 214.

The reference design point used in generating reference PPA 214 of thememory component includes a first set of values (the reference values)for technology node parameters (i.e., node geometry, foundry, and nodevariants) and memory parameters (e.g., memory compiler, memorydescription that includes number of read ports, number of write ports,type of memory (SRAM or register file), type of bit-cell used (highdensity of high speed), memory vendor, and other memory properties suchcolumn mux, redundancy, built-in-self-test, number of banks, powermanagement, and the like). For the parameters of PVT conditions, thereference design point also includes values corresponding to the firstset of values of technology node parameters and memory parameters.Often, the PVT conditions are standard values. For example, if thereference values for the technology node parameters and memoryparameters are 45 nm TSMC HPM process technology with a single portread-write memory component with high density bit cell and a specificmemory vendor, the parameters for PVT conditions will include nominalvalues associated with the 45 nm TSMC HPM process technology with asingle port read-write memory with high density memory bit cell and thespecific memory vendor. In one embodiment, the nominal values for theseparameters are room temperature (e.g., 25 C), nominal supply voltage(e.g., 1V), and nominal process corner (e.g., typical process corner).

The trial design point used for estimating trial PPA of the memorycomponent is analogous to the trial design point used for estimatingtrial PPA of the logic components described above with reference to FIG.4, except that it uses memory parameters instead of library group andlibrary variants. It includes a second set of values (the trial values)for technology node parameters and memory parameters. For the parametersof the PVT conditions, the trial design point uses the same values asthe reference design point.

Technology memory PPA database 292M is a subset of PPA database 290. Thetechnology memory PPA database includes evaluated PPA metrics oftechnology memory test components at various design points. Thetechnology memory test components include a set of predefined memorytest components that are evaluated and their PPAs stored in the PPAdatabase 292M. If a test component is identical to the memory componentbeing analyzed, that particular test component is selected. Otherwise,the optimization engine creates or builds in real-time a memory testcomponent that matches the memory component being optimized andestimates its PPA values in real-time as well. These PPA values areinitially used for technology memory scaling of the memory component.Simultaneously, the engine launches a simulation to evaluate PPA metricsfor all combinations of the memory component's parameters and updatesthe PPA database.

The technology memory PPA database is generated by characterizingvarious technology memory test components at different design points.One method of characterizing the technology memory test components isanalogous to the method described above with reference to technologylogic test components. One difference between technology logic testcomponents and technology memory test components is that while logictest components are typically not the same as the logic component beingoptimized, memory test components typically are identical to the memorycomponent being optimized. In one embodiment, each memory component hasnumerous implementations based on the parameters associated with thememory. Each parameter has two or more values associated with it,resulting in n1. n2. n3 . . . nm combination, where n_(i) is the numberof values associated with the ith memory parameter and there are mparameters. Each one of these combinations can be a trial design pointfor the memory component.

The technology memory scaling process begins with an identification (orbuilding) of a candidate memory from the technology memory PPA database292M that is equivalent to the memory component being optimized. In 710,the characteristics of the memory component are used to identify orbuild the memory test component. Only those candidate test componentsthat match the properties of the memory component being optimized areconsidered. For example, if the memory component is a single port readwrite memory with 4096 words and 64 bits and no redundancy, and thetarget technology is TSMC 28HPM, step 710 will look for all memories inthe database 292M that match these parameters. If none of the existingmemory components of the database 292M match the memory component beingoptimized, the engine in real-time builds or creates a memory componentthat is identical to the memory component being optimized.

The technology memory scaling module accesses technology memory PPAdatabase 292M for identifying the evaluated PPA metrics of theequivalent memory test component at the reference and trial designpoints. The module then determines 712 a technology memory scale factorfor the technology memory test component, for scaling from the referencedesign point to the trial design point. In one embodiment, the moduleuses the evaluated PPA metrics of the technology memory test componentat the reference design point and at the trial design point to determinethe technology memory scale factor of the technology memory testcomponent. For example, the module identifies a first value for theevaluated PPA metric of the technology memory test component at thereference design point and a second value at the trial design point. Themodule then computes a ratio of the first and second values to determinethe technology memory scale factor for the technology memory testcomponent. For example, a ratio between first and second values of PPAmetrics might be 1.5.

The technology memory scale factor determined for the technology memorytest component is then applied 714 to the reference PPA of the memorycomponent to generate an estimated technology trial memory PPA of thememory component at the trial design point. For example, if thereference area PPA for the memory component is 2000 μm² and if thememory scale factor is 1.5, the estimated technology trial memory areaPPA of the memory component at the trial design point is 3000 μm² (i.e.,2000 multiplied by 1.5). As another example, if the referenceperformance PPA (e.g., operating frequency) for the memory component is1 GHz and if the memory scale factor is 1.25, the estimated technologytrial memory performance PPA of the memory component at the trial designpoint is 0.8 GHz (1 GHz divided by 1.25).

FIG. 8 is a block diagram of the PVT memory scaling shown in FIG. 3,according to one embodiment. PVT memory scaling module 374M receives thememory component to estimate component-level trial memory PPA metric forthe memory component at a trial design point. The PVT memory scalingmodule estimates the component-level trial memory PPA metric byreferring to PVT memory PPA database 294M. The module also receives aPPA metric 720 that is the estimated technology trial memory PPA metricby the technology memory scaling module for the received memorycomponent.

In one embodiment, PVT memory scaling accounts for any differences inone or more of: process, voltage or temperature values (i.e., operatingconditions or PVT conditions). Technology memory scaling, as describedabove with reference to FIG. 7, accounts for differences in technologynode parameters and memory parameters. In other words, technology memoryscaling first performs scaling of the memory components over technologynode parameters and memory parameters, and PVT memory scaling thenperforms scaling over PVT conditions. A PVT memory scale factorcalculator is used for calculating PVT memory scaling. This is analogousto the PVT logic scale factor calculator, but it uses the technology,memory bit cell and reference PVT as inputs to compute a scale factorfor a target PVT.

The received PPA metric 720 is an estimated technology memory PPA metricfor the memory component at the trial design point. The variousparameters of the design point associated with the PPA metric 720 arethe same as the trial design point used in technology memory scalingmodule 372M. Memory components and logic components use differentparameters for design points. However they do share some parameters, andthese common parameters will be used by the technology memory scalingmodule 372M. For example, memory and logic components share thetechnology node parameters. The parameters of the trial design pointinclude the trial values (described above with reference to FIG. 7) fortechnology node parameters and memory parameters, and standard (ornominal) values for the PVT conditions.

The trial design point of the PVT memory scaling used for estimatingtrial PPA of the memory component includes the same second set of valuesfor technology node parameters and memory parameters as used in thetrial design point used for technology memory scaling. The trial designpoint of the PVT memory scaling includes trial values for the parametersof PVT conditions.

PVT memory PPA database 294M is a subset of PPA database 290. The PVTmemory PPA database includes evaluated PPA metrics of PVT memory testcomponents at various design points. The PVT memory test components thatare used in generating the PVT memory PPA database include differenttest components for different sets of technology node parameters andmemory parameters. Accordingly, there can be a different PVT memory testcomponents for each combination of technology node parameters and memoryparameters.

The design points at which the PPA metrics of the PVT memory PPAdatabase are evaluated include all possible values for technology nodeparameters, memory bit cells, and PVT conditions. The memory bit cellsused include bit cells for various combinations of memory compiler,memory vendor, and other memory parameters. In addition, the PVT logicPPA database 294M can include evaluated PPA metrics of memory peripherallogic that is used to access the memory array. Memories can be broken upinto two sections—memory array and peripheral logic, where theperipheral logic is to access the memory array. PVT memory scaling isbased on scaling both these memory components. PVT scaling for thememory peripheral logic uses the same technique as PVT logic scalingdescribed above with reference to FIG. 5. However, PVT scaling for thememory array is based on simulations of the memory bit cell and isdescribed below with reference to FIG. 8. Parameters for the bit cellinclude technology node, number of read-write ports in the bit cell, andthe type of bit cell (high density or high speed).

One method of generating the PVT memory PPA database is to firstidentify the number of unique PVT memory test components (e.g., F) thatare needed based on the number of unique combinations of technology nodeparameters and memory parameters. For example, there can be F number ofmemory bit cells. In such exemplary embodiment, each of the F number ofbit cells is evaluated at different combinations of parametersassociated with the PVT conditions. Given that there are threeparameters associated with the PVT conditions (i.e., process corner,supply voltage, and temperature), each bit cell might be evaluated N³times, where N is the number of possible values for each of the threeparameters. In one embodiment, a test memory circuit is designed toemulate a power consumption of the memory bit array, where the testmemory circuit is designed based on the technology node parameters andmemory parameters of the memory bit array. Each memory bit cell has adifferent corresponding memory test component for emulating powerconsumption of the bit array.

The PVT memory PPA database is generated by characterizing various PVTmemory test components at different design points. One method ofcharacterizing the memory test components (e.g., memory bit cell) is bysimulating the bit cell to evaluate its PPA metrics at different designpoints. The PPA metrics that are evaluated can include, for example,read time, write time, active power consumption, leakage powerconsumption, and area. Each of the above-listed bit cell PPA metrics isevaluated for various values of parameters associated with the PVTconditions. For example, bit cell PPA metrics can be evaluated atdifferent junction temperatures, process corners, and supply voltage.

The PVT memory scaling process begins by the PVT memory scaling moduleselecting 810 an appropriate PVT memory test component (e.g., anappropriate memory bit cell). The appropriate memory bit cell isselected based on the memory parameters for the memory component. Themodule then accesses the PVT memory PPA database to identify two sets ofPPA metrics of the selected bit cell. The first set of valuescorresponds to the standard (or nominal) values of the parameters of thePVT conditions associated to the received PPA 720 from the technologymemory scaling. The second set of values corresponds to the trial valuesof the parameters of the PVT conditions associated with the trial designpoint.

The module then determines 812 a PVT memory scale factor for the memoryarray based on the first set of values and the second set of values. Forexample, the module computes a ratio of the first and second values(e.g., 1.1) to determine the PVT memory scale factor for the bit cell.For the memory peripheral logic, a PVT logic test component is selectedbased on the channel length and threshold voltage of the devices used inthe memory peripheral logic. When computing a memory power PPA, thepower PPA is broken into two components—array and periphery. Eachcomponent is scaled separately and the results combined. The memoryperformance PPA is often dominated by the peripheral logic, so typicallyit is sufficient to perform PVT logic scaling of the peripheral logic toscale the memory component.

The PVT memory scale factor determined for the PVT memory test componentis then applied to scale 814 the received technology memory PPA 720 ofthe memory component to generate an estimated trial memory PPA of thememory component at the trial design point. For example, if the receivedtechnology area PPA for the memory component is 3000 μm² and if the PVTmemory scale factor is 1.1, the estimated trial memory area PPA of thememory component after PVT memory scaling at the trial design point is3300 μm² (i.e., 3000 multiplied by 1.1). As another example, if thereceived technology power PPA (e.g., dynamic power) for the memorycomponent is 1 mA and if the PVT memory scale factor is 1.2, theestimated trial memory power PPA of the memory component after PVTmemory scaling at the trial design point is 1.2 mA (i.e., 1 multipliedby 1.2). The estimated trial memory PPA at the output of PVT memoryscaling module is a trial memory PPA of the memory component aftercombining the technology memory scaling and the PVT memory scaling.

In some embodiments, the estimation engine can find all memory instancesthat meet or exceed the target memory PPA received for the memoryportion of the IC design. One method of identifying all memory instancesthat meet or exceed the target memory PPA is to first identify a list oftest memory components used in building the memory PPA database (i.e.,292M and 294M) by matching the properties of the memory component beingoptimized. Then for each identified test memory component, the methodevaluates the trial PPA for a given target conditions and then selectthe optimal test component based on a given optimization criteria.

FIG. 9 is a block diagram of a special-purpose computing device that canoptimize the IC design, according to one embodiment. In one exemplaryembodiment, a non-transitory computer-readable medium (e.g.,non-volatile memory 918) can store instructions which when executedimplement the optimization process of the IC design. Alternatively, arepresentation of the IC design can be stored in the non-transitorycomputer-readable medium. The representation can be at a behaviorallevel, register transfer level, logic component level, transistor level,and layout geometry-level of the IC design.

In some embodiments, computer 900 comprises an interconnect or bus 902(or other communication means) for transmission of data. Computer 900can include a processing means such as one or more processors 904coupled with bus 902 for processing information. Processors 904 cancomprise one or more physical processors and/or one or more logicalprocessors. While bus 902 is illustrated as a single interconnect forsimplicity, it is understood that bus 902 can represent multipledifferent interconnects or buses. Bus 902 shown in FIG. 9 is anabstraction that represents any one or more separate physical buses,point to point connections, or both connected by appropriate bridges,adapters, controllers and/or the like.

In some embodiments, computer 900 further comprises a random accessmemory (RAM) or other dynamic storage device depicted as main memory 912for storing information and instructions to be executed by processors904. Main memory 912 can include an active storage of applicationsincluding a browser application for using in network browsing activitiesby a user of computer 900. Main memory 912 can further include certainregisters or other special purpose memory.

Computer 900 can also comprise a read only memory (ROM) 916 or otherstatic storage device for storing static information and instructionsfor processors 904. Computer 900 can further include one or morenon-volatile memory elements 918 for the storage of certain elements,including, for example, flash memory, a hard disk, solid-state drive.Non-volatile memory elements 918 can store a representation of the ICdesign described above with references to FIGS. 2 through 8, orcomponents within the IC design, can be stored as data. Therepresentation can be at a behavioral level, register transfer level,logic component level, transistor level, and layout geometry-level ofthe IC design.

Computer 900 can comprise transceiver module 920 that is coupled to bus902. Transceiver module 920 can further comprise a transmitter moduleand a receiver module. Transceiver module 920 comprises one or moreports 922 to connect to other devices (not shown).

Computer 900 can also comprise circuit logic 940 coupled to bus 902 andconfigured to detect information from a second device (not shown)coupled through ports 922. Computer 900 can also comprise output display926 and coupled via bus 902. In some embodiments, display 926 caninclude a liquid crystal display (LCD) or any other display technology,for displaying information or content to a user, includingthree-dimensional (3D) displays. Alternatively, display 926 can includea touch screen that can also be part of input device 924. In someenvironments, display 926 can include an audio device, such as a speakerfor providing audio information. Computer 900 can also comprise powerdevice 930 that can comprise a power supply, a battery, a solar cell, afuel cell, or other device for providing or generating power. Any powerprovided by power device 930 can be distributed as required to elementsof computer 900.

While particular embodiments and applications of the present disclosurehave been illustrated and described, it is to be understood that theembodiments are not limited to the precise construction and componentsdisclosed herein and that various modifications, changes and variationsmay be made in the arrangement, operation and details of the method andapparatus of the present disclosure disclosed herein without departingfrom the spirit and scope of the disclosure as defined in the appendedclaims.

What is claimed is:
 1. A non-transitory computer-readable storage mediumstoring executable computer program instructions for estimating a trialPPA (power, performance, area) metric for an integrated circuit designevaluated at a trial design point, the instructions executable by aprocessor and causing the processor to perform a method comprising:receiving an integrated circuit design, the integrated circuit designcomprising a logic portion and a memory portion, the logic portionrepresented by a count of logic gates; estimating a trial PPA metric forthe logic portion evaluated at the trial design point, comprising:accessing a reference PPA metric for an equivalent test component forthe logic portion, the equivalent test component based on the count oflogic gates for the logic portion and the reference PPA metric evaluatedat a reference design point; determining a logic scale factor for thelogic portion, the logic scale factor based on: scaling from (a) thereference design point to (b) the trial design point, of the equivalenttest component for the logic portion; and applying the logic scalefactor to the reference PPA metric to determine the trial PPA metric atthe trial design point; estimating a trial PPA metric for the memoryportion evaluated at the trial design point; and combining the trial PPAmetric for the logic portion and the trial PPA metric for the memoryportion to obtain a trial PPA metric for the integrated circuit designevaluated at the trial design point.
 2. The non-transitorycomputer-readable storage medium of claim 1, wherein the logic portionof the integrated circuit design is represented by the count of logicgates without specifying any actual logic components, and determiningthe logic scale factor does not depend on the actual logic componentscontained in the logic portion.
 3. The non-transitory computer-readablestorage medium of claim 1, wherein the logic portion of the integratedcircuit design is represented by the count of logic gates without anyRTL representation of the logic portion, and determining the logic scalefactor does not depend on any RTL representation of the logic portion.4. The non-transitory computer-readable storage medium of claim 1,wherein estimating the trial PPA metric for the logic portion occursbefore synthesis of an RTL representation of the logic portion.
 5. Thenon-transitory computer-readable storage medium of claim 1, whereinestimating the trial PPA metric for the logic portion occurs at an earlydesign stage before an actual logic design of the logic portion isavailable.
 6. The non-transitory computer-readable storage medium ofclaim 1, wherein the PPA metric includes at least one of: dynamic power,leakage power, operating frequency, and die area.
 7. The non-transitorycomputer-readable storage medium of claim 1, wherein the count of logicgates representing the logic portion is a count of a single type oflogic gate.
 8. The non-transitory computer-readable storage medium ofclaim 7, wherein the single type of logic gate is either a NAND logicgate or a NOR logic gate.
 9. The non-transitory computer-readablestorage medium of claim 1, wherein the count of logic gates representingthe logic portion includes a count of NAND logic gates or a count of NORlogic gates.
 10. The non-transitory computer-readable storage medium ofclaim 1, wherein the equivalent test component to the logic portion isdetermined based on a type of logic gate used in the count of logicgates representing the logic portion.
 11. The non-transitorycomputer-readable storage medium of claim 1 wherein the logic scalefactor for the logic portion comprises a technology scale factor thataccounts for differences in technology node and library.
 12. Thenon-transitory computer-readable storage medium of claim 1 wherein thelogic scale factor for the logic portion comprises a PVT scale factorthat accounts for differences in PVT conditions.
 13. The non-transitorycomputer-readable storage medium of claim 1, wherein the memory portionis represented by a specified memory component, and estimating a trialPPA metric for the memory portion evaluated at the trial design pointcomprises: accessing a reference PPA metric for the memory componentdesign evaluated at a reference design point; determining a scale factorfor the memory component, the scale factor based on: scaling from (a)the reference design point to (b) the trial design point, of anequivalent test component to the memory component; and applying thescale factor to the reference PPA metric to determine the trial PPAmetric for the memory portion at the trial design point.
 14. Thenon-transitory computer-readable storage medium of claim 1 wherein: theintegrated circuit design comprises a plurality of logic portions and aplurality of memory portions; estimating a trial PPA metric for thelogic portion evaluated at the trial design point comprises estimating atrial PPA metric for each of the logic portions evaluated at the trialdesign point; estimating a trial PPA metric for the memory portionevaluated at the trial design point comprises estimating a trial PPAmetric for each of the memory portions evaluated at the trial designpoint; and combining the trial PPA metric for the logic portion and thetrial PPA metric for the memory portion comprises combining the trialPPA metrics for all of the logic portions and the trial PPA metrics forall of the memory portions to obtain a trial PPA metric for theintegrated circuit design evaluated at the trial design point.
 15. Thenon-transitory computer-readable storage medium of claim 14, wherein theintegrated circuit design is a design for a system-on-chip (SoC).
 16. Anon-transitory computer-readable storage medium storing executablecomputer program instructions for recommending a design point for anintegrated circuit design, the instructions executable by a processorand causing the processor to perform a method comprising: receiving anintegrated circuit design, the integrated circuit design comprising alogic portion and a memory portion, the logic portion represented by acount of logic gates; receiving a target PPA metric for the integratedcircuit design; estimating trial PPA metrics for the integrated circuitdesign evaluated at a plurality of trial design points according to thecomputer program instructions of claim 1; and based on the estimatedtrial PPA metrics and the target PPA metric, recommending a trial designpoint for the integrated circuit design.
 17. The non-transitorycomputer-readable storage medium of claim 16, wherein the plurality oftrial design points includes design points at different processfoundries, different node geometries and/or different process variants;and recommending the trial design point comprises recommending fromamong the different process foundries, different node geometries and/ordifferent process variants.
 18. The non-transitory computer-readablestorage medium of claim 16, wherein the plurality of trial design pointsincludes design points using different libraries, the differentlibraries include libraries from different library vendors and/or withdifferent numbers of tracks; and recommending the trial design pointcomprises recommending from among the different library vendors and/orwith different numbers of tracks.
 19. The non-transitorycomputer-readable storage medium of claim 16, wherein the method furthercomprises: receiving design constraints on the integrated circuitdesign, wherein recommending a trial design point is further based onmeeting said design constraints.
 20. A non-transitory computer-readablestorage medium storing executable computer program instructions foroptimizing a design point for an integrated circuit design, theinstructions executable by a processor and causing the processor toperform a method comprising: receiving an integrated circuit design, theintegrated circuit design comprising a logic portion and a memoryportion, the logic portion represented by a count of logic gates;receiving a target PPA metric for the integrated circuit design;estimating trial PPA metrics for the integrated circuit design evaluatedat a plurality of trial design points according to the computer programinstructions of claim 1; and iteratively optimizing the trial designpoint, based on the estimated trial PPA metrics and the target PPAmetric.